Current Result Document :
| 한글제목(Korean Title) |
MIMO Detection을 위한 효율적인 List Sphere Decoder의 구조 제안 |
| 영문제목(English Title) |
Efficient VLSI Architecture of List Sphere Decoder for MIMO Detection |
| 저자(Author) |
이진
박신종
Jin Lee
Sin-Chong Park
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| 원문수록처(Citation) |
VOL 16 NO. 01 PP. IB ~ 0008 (2006. 04) |
한글내용
(Korean Abstract) |
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영문내용
(English Abstract) |
Since finding the nearest point in a lattice for multi-input multi-output (MIMO) channels is NP-hard, simplified algorithms such as sphere decoder (SD) have been proposed. List sphere decoder (LSD), which is a modified version of SD, allows soft information to be extracted for channel decoding and iterative detection/decoding. In this paper, recently proposed efficient methods for reducing the computational complexity of SD and LSD with depth-first tree searching are summarized. Numerous simulations have been carried out and comparison has been made based on the average number of processing cycles. We also present two efficient schemes which can decrease hardware complexity without significant performance degradation, restricted list updating in LSD and restricted node storing at each tree level. Generating soft information increases the computational complexity for selecting a specific number of candidate lattice points. In this paper an efficient pipelined VLSI architecture for LSD is presented and its complexity is analyzed. The architecture is constructed with three pipeline stages, two stages for metric calculation units (MCU) and one stage for metric enumeration unit (MEU). It also has three storage units and list units for three successive input MIMO vectors. The pipeline can increase the operating clock frequency and keep one-node-per-cycle policy, so that the average throughput can enhance according to the increment of the clock frequency.
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